library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_UNSIGNED.ALL;

entity lcdc is
	Port(
	clk:		in std_logic;
	ma:			out std_logic_vector(14 downto 0);
	md:			inout  std_logic_vector(7 downto 0);
	rw,cs,oe:		out std_logic;
	cp1,cp2,m,frm:	out std_logic;
	do:			out std_logic_vector(3 downto 0);
	databus:	in std_logic_vector(7 downto 0);
	cpuctrl: 	in std_logic_vector(1 downto 0);
	cpulatch:	in std_logic
	);

 -- attribute pin_assign : string;
 -- attribute pin_assign of ma: signal is "41,76,43,71,69,72,74,46,45,48,47,51,52,53,55";
 -- attribute pin_assign of md: signal is "67,66,63,62,61,57,56,54";
 -- attribute pin_assign of cs: signal is "68";
 -- attribute pin_assign of oe: signal is "70";
 -- attribute pin_assign of rw: signal is "75";
 -- attribute pin_assign of do: signal is "23,20,21,18";
 -- attribute pin_assign of m:  signal is "17";
 -- attribute pin_assign of frm:signal is "14";
 -- attribute pin_assign of cp2:signal is "15";
 -- attribute pin_assign of cp1:signal is "12";
 -- attribute pin_assign of databus:signal is "4,3,2,1,84,83,82,81";
 -- attribute pin_assign of cpuctrl:signal is "6,5";
 -- attribute pin_assign of cpulatch:signal is "10";
 -- attribute pin_assign of clk:signal is "9";



end lcdc;

architecture Behavioral of lcdc is

	signal	div:		std_logic_vector(3 downto 0);
	signal	icp1:	std_logic;
	signal	icp2:	std_logic;
	signal	b:		std_logic;
	signal	x:		std_logic_vector(5 downto 0);
	signal	y:		std_logic_vector(7 downto 0);
	signal	q:		std_logic_vector(7 downto 0);
	signal 	iadr:	std_logic_vector(13 downto 0);
	signal	ima:		std_logic_vector(14 downto 0);
	signal	ifrm:	std_logic;
	signal	im:		std_logic;
	signal 	ibsel:	std_logic;
	signal	iwait:	std_logic;
	signal	outwait:	std_logic;
	signal	outbsel:	std_logic;
	signal  	cpuadr:	std_logic_vector(13 downto 0);
	signal  	cpudat:	std_logic_vector(7 downto 0);
	signal 	cpuy:	std_logic_vector(7 downto 0);
	signal 	cpux:	std_logic_vector(5 downto 0);
	signal	preadr:std_logic_vector(6 downto 0);


 begin


	process(cpulatch,cpuctrl)
	begin
 	  if(cpulatch'event and cpulatch='1') then
	    if(cpuctrl="10") then
	      cpuy<=databus;
	    elsif(cpuctrl="01") then 
	      if(databus(5 downto 0)=40) then 
		   cpux<="101110";
		   if(cpuy=191) then cpuy<="00000000";
		   else cpuy<=cpuy+1;
		   end if;
		 elsif(databus(5 downto 0)=41) then
		   cpux<="101111";
		   if(cpuy=191) then cpuy<="00000000";
		   else cpuy<=cpuy+1;
		   end if;
		 elsif(databus(5 downto 0)>41) then 
		   cpux<=databus(5 downto 0)-2;
		 else
	        cpux<=databus(5 downto 0);
		  end if;
	    elsif(cpuctrl="00" and outwait='0') then
	      cpudat<=databus;
		 cpuadr<=(191-cpuy)&(63-cpux);
	    end if;
	  end if;
	end process;


  	process(clk)
	begin
	  if(clk'event and clk='1') then
	    if(div="1000")	then --16•ªŽü
		 if(icp2='0') then
		   icp1 <= '0';
		   if(b='1') then
		     q<=md;
			if(x="101111") then -- x=47‚È‚ç
			  if(y="10111111") then
			    y<="00000000";
			    x<="000000";
			  else
			    y<=y+1;
			    x<="000000";
			  end if; 
			else
			  x<=x+1;
			end if;
		   else
		     q(7 downto 4)<=q(3 downto 0);
		   end if;
		   b<= not b;
		 else
		   if(b='1' and x=0) then
		     icp1<='1';
		   end if;
		 end if;
		 icp2<=not icp2;
		 div<="0000";
	    else 
		 div<=div+1;
	    end if;
	  end if;
	end process;
	cp1<=icp1;
	cp2<=icp2;
	do<=q(7 downto 4);
	iadr <= y & x;

		   
	process(clk)
	begin
 	  if(clk'event and clk='1') then
	    if(b='1' and icp2='0') then
	      if(div="0110") then 
	 	   ibsel<='1';
		 elsif(div="0100") then
		   iwait<='1';
		 end if;
	    elsif(b='0' and icp2='1' and div="0001") then
	   	iwait<='0';
         elsif(b='0' and icp2='1' and div="0000") then
	     ibsel<='0';
	    end if;
 	  end if;
	end process;


	process(clk)
	begin
 	  if(clk'event and clk='1') then
   	    if(b='0') then
   	      if(div="0101") then 
	        outbsel<='1';
		 elsif(div="0111") then 
		   outbsel<='0';
		 elsif(div="0011" and preadr/=cpuadr(6 downto 0)) then 
		   outwait<='1';
		 elsif(div="1000" and outwait='1') then
	        outwait<='0';
		   preadr<=cpuadr(6 downto 0);
		 end if;
	    end if;
	  end if;

	end process;

  	process(iwait,outwait,iadr,cpuadr,cpudat,x,y)
	begin
	  if(iwait='1') then
	    ima<="1"&iadr(13 downto 6)&(63-iadr(5 downto 0));
	    md <="ZZZZZZZZ";
	  elsif(outwait='1') then
	    ima<="1"&cpuadr(13 downto 0);
	    md <=cpudat;
	  else
	    ima<="000000000000000";
	    md<="00000000";
	  end if;
	end process;

 	ma<=ima;
	rw<=not (outbsel and outwait);
	cs<=not (iwait or outwait);
	oe<=not (ibsel and iwait);

	process(clk)
	begin
	  if(clk'event and clk='1') then
	    if(iadr="00000000000001"and b='0' and div="1000") then
		 ifrm<='1';
	    elsif(iadr="00000001000001" and b='0' and div="1000") then
		 ifrm<='0';
	    end if;
	  end if;
	end process;

	process(ifrm)
	begin
	  if(ifrm'event and ifrm='1') then
	    im<=not im;
	  end if;
	end process;

	frm<=ifrm;
	m<=im;

end Behavioral;