library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clock_counter is
    Port (
	xclk	:	in	std_logic;
	hour1:	out	std_logic_vector(3 downto 0);
	hour2:	out	std_logic_vector(3 downto 0);
	min1	:	out	std_logic_vector(3 downto 0);
	min2	:	out	std_logic_vector(3 downto 0);
	sec1	:	out	std_logic_vector(3 downto 0);
	sec2	:	out	std_logic_vector(3 downto 0);
	cpu_clk:	in	std_logic;
	cpu_idat:	in	std_logic;
	cpu_odat:	out	std_logic;
	cpu_rw:	in 	std_logic;
	cpu_clr:	in	std_logic
   
     );

  attribute pin_assign : string;                     -- Assigns Pins
  attribute pin_assign of xclk	: signal is "9";
  attribute pin_assign of sec2 	: signal is "11,14,13,19";
  attribute pin_assign of sec1	: signal is "18,20,22,24";
  attribute pin_assign of min2	: signal is "26,28,33,36";
  attribute pin_assign of min1 	: signal is "35,38,37,39";
- attribute pin_assign of hour2 	: signal is "40,42,43,44";
- attribute pin_assign of hour1 	: signal is "1,2,3,4";
  attribute pin_assign of cpu_clk	: signal is "8";
  attribute pin_assign of cpu_idat	: signal is "7";
  attribute pin_assign of cpu_odat	: signal is "6";
  attribute pin_assign of cpu_rw	: signal is "5";
  attribute pin_assign of cpu_clr	: signal is "12";

end clock_counter;

architecture Behavioral of clock_counter is



signal	devider:	std_logic_vector(23 downto 0);
signal	ihour1:	std_logic_vector(3 downto 0);
signal	ihour2:	std_logic_vector(3 downto 0);
signal	imin1:	std_logic_vector(3 downto 0);
signal	imin2:	std_logic_vector(3 downto 0);
signal	isec1:	std_logic_vector(3 downto 0);
signal	isec2:	std_logic_vector(3 downto 0);
signal	odata:	std_logic;
signal	phase:	std_logic_vector(4 downto 0);

begin

	process(xclk)
	begin
	  if(xclk'event and xclk='1') then

	  if(cpu_rw='1') then 
	     case phase is                              
		      when "00000" => ihour1(3)<='0';
		      when "00001" => ihour1(2)<=cpu_idat;
		      when "00010" => ihour1(1)<=cpu_idat;
		      when "00011" => ihour1(0)<=cpu_idat;
		      when "00100" => ihour2(3)<=cpu_idat;
		      when "00101" => ihour2(2)<=cpu_idat;
		      when "00110" => ihour2(1)<=cpu_idat;
		      when "00111" => ihour2(0)<=cpu_idat;
		      when "01000" => imin1(3) <=cpu_idat;
		      when "01001" => imin1(2) <=cpu_idat;
		      when "01010" => imin1(1) <=cpu_idat;
		      when "01011" => imin1(0) <=cpu_idat;
		      when "01100" => imin2(3) <=cpu_idat;
		      when "01101" => imin2(2) <=cpu_idat;
		      when "01110" => imin2(1) <=cpu_idat;
		      when "01111" => imin2(0) <=cpu_idat;
  		      when others  =>    
	    end case;	
	    isec1<="0000";
	    isec2<="0000";			
	    devider<="000000000000000000000001";
	  else

	    if(devider=12800000) then 
	      devider<="000000000000000000000001";



		 if(isec2=9) then 
	        isec2<="0000";
		   if(isec1=5) then 
		     isec1<="0000";
			if(imin2=9) then 
			  imin2<="0000";
			  if(imin1=5) then
			    imin1<="0000";
			    if(ihour1=2 and ihour2=3) then 
			      ihour1<="0000";
				 ihour2<="0000";
			    elsif(ihour2=9) then
			      ihour2<="0000";
				 ihour1<=ihour1+1; 
			    else ihour2<=ihour2+1;
			    end if; 
			  else imin1<=imin1+1;
			  end if;
			else imin2<=imin2+1;
			end if;
		   else isec1<=isec1+1;
		   end if;
		 else isec2<=isec2+1;
		 end if;




	    else 
	      devider<=devider+1;
	    end if;
	  end if;
	  end if;
	end process;

     hour1<=ihour1;
     hour2<=ihour2;
     min1<=imin1;
     min2<=imin2;
     sec1<=isec1;
     sec2<=isec2;



	process(cpu_clk)
	begin
	  if(cpu_clk'event and cpu_clk='1') then
		if (cpu_clr='1') then  phase<="00000";
		else phase<=(phase+1); 
		end if;

	     case phase is                              
		      when "00000" => odata<=ihour1(3);
		      when "00001" => odata<=ihour1(2);
		      when "00010" => odata<=ihour1(1);
		      when "00011" => odata<=ihour1(0);
		      when "00100" => odata<=ihour2(3);
		      when "00101" => odata<=ihour2(2);
		      when "00110" => odata<=ihour2(1);
		      when "00111" => odata<=ihour2(0);
		      when "01000" => odata<=imin1(3);
		      when "01001" => odata<=imin1(2);
		      when "01010" => odata<=imin1(1);
		      when "01011" => odata<=imin1(0);
		      when "01100" => odata<=imin2(3);
		      when "01101" => odata<=imin2(2);
		      when "01110" => odata<=imin2(1);
		      when "01111" => odata<=imin2(0);
		      when "10000" => odata<=isec1(3);
		      when "10001" => odata<=isec1(2);
		      when "10010" => odata<=isec1(1);
		      when "10011" => odata<=isec1(0);
		      when "10100" => odata<=isec2(3);
		      when "10101" => odata<=isec2(2);
		      when "10110" => odata<=isec2(1);
		      when "10111" => odata<=isec2(0);

  		      when others => odata<='0';    
	    end case;				
	  end if;
	end process;

	cpu_odat<=odata;
End Behavioral;